In the Information Age, data is stored, processed, and transmitted almost exclusively in a digital format. Speech, music, video, text, pictures, etc., are digitized and represented as a series of bits of information in the form of 0's and 1's. This information is thusly converted into a digital format so that it can be readily recognized and processed by a computer system. Basically, a computer system is comprised of multiple integrated circuits, each of which can contain upwards of millions of transistors. These transistors can be either turned off (i.e., "0") or turned on (i.e., "1") in order to accomplish a given task according to a computer program.
A "clock" is used to regulate the speed at which the integrated circuits operate. Initially, computer systems ran at extremely slow rates of speed (i.e., low clock speeds). However, due to rapid advances in semiconductor technology, computers are becoming much faster and more powerful. Likewise, the peripheral devices (e.g., hard disk drives, modems, etc.) supporting the computer systems are becoming faster. Furthermore, the transmission mediums (e.g., twisted pair wires, coaxial cables, fiber optics, etc.) for conveying data in a computer network are experiencing greater transmission rates and throughput. Indeed, the trend is towards ever increasing clock speeds.
One side-effect from the quest for attaining faster clock speeds is the proliferation of devices and transmission mediums that operate at different clock speeds. For example, an older computer system might run at a slower clock speed (e.g., 33 MHz), whereas a newer computer system might run at a much faster clock speed (e.g., 200 MHz). In many instances, there might be a need for the two computer systems to communicate with each other. However, there is a problem with interfacing the two computers, which is attributed to the fact that they are incompatible because they run at different speeds. Moreover, this problem is further exacerbated if the medium conveying the data were to have yet a different speed at which data is to be transmitted. In which case, one must synchronize the exchange of data between the computer systems with that of the transmission medium. Moreover, the format of the data itself might have an intrinsic bandwidth, different from that of the computer system or transmission medium. For example, one application might be called upon to accept a 5 MHz video signal for display upon a 120 MHz computer system via a 2 MHz T1 cable. Hence, there must be some way to handle the exchange of data between two devices and/or transmission lines having different clock speeds, without inducing any errors.
This problem posed by devices operating at different clock speeds is quite prevalent. One contributing factor lies with the fact that there exists many various industry standards and protocols. These standards and protocols usually specify a particular speed of operation. Often, the speed set forth by one standard is not compatible with that of another standard. Furthermore, upgrades might cause clock conflicts. In addition, one might desire versatility in a computer system. In which case, the computer system should be adaptable so that it can interface with a host of other devices operating at various clock speeds. Hence, in order to achieve compatibility, upgradability, and adaptability between devices running at different clock speeds, there must be some mechanism for handling the exchange of data between these devices.
FIG. 1 shows a prior art method for handling two different clock speeds. Data is initially input to a flip-flop 101. Flip-flop 101 is clocked at a clock speed of CLK1. The output from flip-flop 101 is then input to logic block 102, such as a FIFO memory. The output from logic block 102 is input to a second flip-flop 103, running at a different clock speed CLK2. The problem with this approach is that the phase differences between the two clocks, CLK1 and CLK2, might result in data errors. Typically, data is sampled at the rising edges of a clock signal. If CLK2 were faster than CLK1, a phase difference (.o slashed.) would occur at some points. Due to this difference in phase, the data would be latched at different times, thereby resulting in read errors. In other words, data is constantly varying over time, and the data existing at time t.sub.1 is not the same as the data existing at time t.sub.2.
Thus, there is a need for an apparatus and method of facilitating the exchange of digital data between two different clock domains. The present invention offers an elegant, efficient solution that preserves data integrity, irrespective of the clock phases. These and other advantages of the present invention will become apparent within discussions of the present invention herein.